module fifo_hier_bench ();

    reg     [63:0]  data_in;
    reg             data_in_valid;
    reg             pop_fifo;
    
    wire    [63:0]  data_out;
    wire            fifo_empty, fifo_full, data_out_valid;
    wire            clk;

    fifo_hier fifo_hier0 (
        .data_out(data_out), .fifo_empty(fifo_empty), .fifo_full(fifo_full),.data_out_valid(data_out_valid),
        .data_in(data_in), .data_in_valid(data_in_valid), .pop_fifo(pop_fifo)   );

    assign  clk = fifo_hier0.clk_generator.clk;
    integer cycle_count;
    initial
    begin

        $dumpvars;
        $display($time, " << Starting the Simulation >>");

        data_in = {16{4'b0000}};
        data_in_valid = 0;
        pop_fifo = 0;
        cycle_count = 0;

        #600    data_in_valid = 1;
        #500    data_in_valid = 0;
        #500    pop_fifo =1;
        #300    data_in_valid = 1;

    end

    always @ (negedge clk)
    begin
        cycle_count = cycle_count+1;
        data_in = cycle_count*17;
        if (cycle_count>8)
        begin
            $finish;
        end
    end

    always @ (posedge clk)
    begin
        $display("cycle=%2d, INPUT=%h, %h|%h|%h|%h, %h|%h|%h|%h, %b%b%b%b, %b%b%b%b, OUTPUT=%h, %s\t%s\t%s\t%s", 
        cycle_count,
        data_in[7:0], 
        fifo_hier0.fifo0.d_bus0[7:0], 
        fifo_hier0.fifo0.d_bus1[7:0], 
        fifo_hier0.fifo0.d_bus2[7:0], 
        fifo_hier0.fifo0.d_bus3[7:0], 
        fifo_hier0.fifo0.q_bus0[7:0], 
        fifo_hier0.fifo0.q_bus1[7:0], 
        fifo_hier0.fifo0.q_bus2[7:0], 
        fifo_hier0.fifo0.q_bus3[7:0], 
        fifo_hier0.fifo0.d0,
        fifo_hier0.fifo0.d1,
        fifo_hier0.fifo0.d2,
        fifo_hier0.fifo0.d3,
        fifo_hier0.fifo0.q0,
        fifo_hier0.fifo0.q1,
        fifo_hier0.fifo0.q2,
        fifo_hier0.fifo0.q3,
        fifo_hier0.fifo0.data_out[7:0],
        data_in_valid?"DATA_IN_VALID":" ",
        data_out_valid?"DATA_OUT_VALID":" ", 
        fifo_hier0.clk_generator.rst?"RESET":" ",
        fifo_empty?"EMPTY":(fifo_full?"FULL":" "));

    end
    endmodule
